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BSI PD IEC TR 61189-5-506:2019

Test methods for electrical materials, printed boards and other interconnection structures and assemblies -- General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501
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BSI PD IEC TR 61189-5-506:2019

Test methods for electrical materials, printed boards and other interconnection structures and assemblies -- General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501

PUBLISH DATE 2019
PAGES 26
BSI PD IEC TR 61189-5-506:2019

This Technical Report is an intercomparison supporting the development of IEC 61189-5-501 in relation to the SIR method. This document sets out to validate the introduction of a new 200-µm gap SIR pattern, and was benched marked against existing SIR gap patterns of 318 µm and 500 µm.

SDO BSI: British Standards Institution
Document Number IEC TR 61189-5-506
Publication Date July 18, 2019
Language en - English
Page Count
Revision Level
Supercedes
Committee EPL/501
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