BSI PD IEC TR 61189-5-506:2019

Current Revision
Test methods for electrical materials, printed boards and other interconnection structures and assemblies -- General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501

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BSI PD IEC TR 61189-5-506:2019

Test methods for electrical materials, printed boards and other interconnection structures and assemblies -- General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501

PUBLISH DATE 2019
PAGES 26
BSI PD IEC TR 61189-5-506:2019

This Technical Report is an intercomparison supporting the development of IECย 61189-5-501 in relation to the SIR method.

This document sets out to validate the introduction of a new 200-ยตm gap SIR pattern, and was benched marked against existing SIR gap patterns of 318ย ยตm and 500ย ยตm.

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