Logo
Login Sign Up
Current Revision

IEC 60191-6-10 Ed. 1.0 b:2003

Mechanical standardization of semiconductor devices - Part 6-10: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Dimensions of P-VSON
Best Price Guarantee
Instant

$131.00

2-5 Days

$131.00

SAVE 10%

$235.80


Sub Total (1 Item(s))

$ 0.00

Estimated Shipping

$ 0.00

Total (Pre-Tax)

$ 0.00


or
International Electrotechnical Commission Logo

IEC 60191-6-10 Ed. 1.0 b:2003

Mechanical standardization of semiconductor devices - Part 6-10: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Dimensions of P-VSON

PUBLISH DATE 2026
PAGES 18
IEC 60191-6-10 Ed. 1.0 b:2003
Mechanical standardization of semiconductor devices - Part 6-10: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Dimensions of P-VSON
IEC 60191-6-10:2003 provides the common outline drawings and dimensions for all types of structures and composed materials of plastic very thin small outline non-lead package (hereinafter called P-VSON).
SDO IEC: International Electrotechnical Commission
Document Number IEC 60191
Publication Date April 1, 2026
Language b - English & French
Page Count 18
Revision Level 1.0
Supercedes
Committee 47D
Publish Date Document Id Type View
April 1, 2026 IEC 60191-6-10 Ed. 1.0 b:2003 Revision
Nov. 1, 2003 Revision