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IEC 60191-6-5 Ed. 1.0 en:2001

Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)
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IEC 60191-6-5 Ed. 1.0 en:2001

Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

PUBLISH DATE 2026
PAGES 16
IEC 60191-6-5 Ed. 1.0 en:2001
Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)
Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch ball grid array the terminal pitch of which is less than or equal to 0,80 mm.
SDO IEC: International Electrotechnical Commission
Document Number IEC 60191
Publication Date April 1, 2026
Language en - English
Page Count 16
Revision Level 1.0
Supercedes
Committee 47D
Publish Date Document Id Type View
April 1, 2026 IEC 60191-6-5 Ed. 1.0 en:2001 Revision
Aug. 1, 2001 Revision