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IEC 61523-1 Ed. 3.0 en:2023

Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
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International Electrotechnical Commission Logo

IEC 61523-1 Ed. 3.0 en:2023

Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)

PUBLISH DATE 2023
PAGES 46
IEC 61523-1 Ed. 3.0 en:2023
Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.
SDO IEC: International Electrotechnical Commission
Document Number IEC 61523
Publication Date Oct. 1, 2023
Language en - English
Page Count 46
Revision Level 3.0
Supercedes
Committee 91
Publish Date Document Id Type View
Oct. 1, 2023 Revision
Oct. 1, 2023 IEC 61523-1 Ed. 3.0 en:2023 Revision