IEC 62530 Ed. 3.0 en:2021

Current Revision
SystemVerilog - Unified Hardware Design, Specification, and Verification Language

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SystemVerilog - Unified Hardware Design, Specification, and Verification Language

PUBLISH DATE 2021
PAGES 1320

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language.

The standard includes support for:

  • behavioral, register transfer level (RTL), and gate-level hardware descriptions;
  • testbench, coverage, assertion, object-oriented, and constrained random constructs;
  • and also provides application programming interfaces (APIs) to foreign programming languages.

This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012. This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.

This publication has the status of a double logo IEEE/IEC standard.

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