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IEC 63011-1 Ed. 1.0 b:2018

Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
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IEC 63011-1 Ed. 1.0 b:2018

Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology

PUBLISH DATE 2018
PAGES 28
IEC 63011-1 Ed. 1.0 b:2018
Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
SDO IEC: International Electrotechnical Commission
Document Number IEC 63011
Publication Date Nov. 28, 2018
Language b - English & French
Page Count
Revision Level 1.0
Supercedes
Committee 47A
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