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IEC 63011-3 Ed. 1.0 b:2018

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via
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IEC 63011-3 Ed. 1.0 b:2018

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

PUBLISH DATE 2018
PAGES 32
IEC 63011-3 Ed. 1.0 b:2018

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via.

IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC.

Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document.

SDO IEC: International Electrotechnical Commission
Document Number IEC 63011
Publication Date Nov. 28, 2018
Language b - English & French
Page Count
Revision Level 1.0
Supercedes
Committee 47A
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