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IEEE 1076.3-1997

IEEE Standard VHDL Synthesis Packages

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IEEE 1076.3-1997

IEEE Standard VHDL Synthesis Packages

PUBLISH DATE 1997

PAGES 52

IEEE 1076.3-1997

Document Information

New IEEE Standard - Superseded. The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.

This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following: a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993. b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the STD_ULOGIC type. c) Standard functions for representing sensitivity to the edge of a signal. d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and that define arithmetic, shift, and type conversion operations on those types. This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.

Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions.


SDO	IEEE: Institute of Electrical and Electronics Engineers
Document Number	1076.3
Publication Date	June 5, 1997
Language	en - English
Page Count	52
Revision Level
Supercedes
Committee	Design Automation

Publish Date	Document Id	Type	View
June 5, 1997	1076.3-1997	Revision

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IEEE 1076.3-1997

IEEE Standard VHDL Synthesis Packages

IEEE 1076.3-1997

Document Information

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