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BSI BS EN 61523-2:2002

Delay and power calculation standards -- Pre-layout delay calculation specification for CMOS ASIC libraries
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BSI BS EN 61523-2:2002

Delay and power calculation standards -- Pre-layout delay calculation specification for CMOS ASIC libraries

PUBLISH DATE 2002
PAGES 42
BSI BS EN 61523-2:2002
Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
SDO BSI: British Standards Institution
Document Number EN 61523-2
Publication Date Sept. 27, 2002
Language en - English
Page Count 42
Revision Level
Supercedes
Committee EPL/501
Publish Date Document Id Type View
Sept. 27, 2002 BS EN 61523-2:2002 Revision