JEDEC JEP122H

Current Revision
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

Best Price Guarantee Sep 1, 2016 English 1 Pages

Sub Total (1 Item(s)) $ 0.00
Estimated Shipping $ 0.00
Total (Pre-Tax) $ 0.00
View in Library
or
Joint Electron Device Engineering Council Solid State Technology Association Logo

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

PUBLISH DATE 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.
Loading...

Failed to load document history.

Publish Date Document Id Type View